Radiation-Tolerant All-Digital PLL/CDR with Varactorless LC DCO in 65 nm CMOS

This paper presents the first fully integrated radiation-tolerant All-Digital Phase-Locked Loop (PLL) and Clock Data Recovery (CDR) circuit for wireline communication applications. Several radiation hardening techniques are proposed to achieve state-of-the-art immunity Single-Event Effects (SEEs) up 62.5 MeV cm2 mg?1 as well tolerance Total Ionizing Dose (TID) exceeding 1.5 Grad. The LC Digitally Controlled Oscillator (DCO) is implemented without MOS varactors, avoiding use of a highly SEE sensitive element. designed operate at reference clock frequencies from 40 MHz 320 or data rates Mbps displays jitter performance 520 fs with power dissipation only 11 mW an FOM ?235 dB.